Dual pipe cache memory with out-of-order issue capability

Abstract

A data cache memory apparatus permits load and store instructions to be issued out-of-order. The apparatus includes a memory. An instruction issue apparatus issues an instruction stream containing store and load instructions. The store instructions are completed in two passes, namely a store allocate pass and a corresponding store commit pass. A cache control is connected to the instruction issue apparatus and the memory and issues store and load addresses to the memory in response to instructions from the instruction issue apparatus. A store history table is connected to the cache control and stores a record of the addresses of the memory where data are to be stored, and thus a record of the store allocate passes issued by the instruction issue apparatus for which no corresponding store commit pass has been completed. The cache control responds to the subsequent corresponding store commit pass to issue the store address to the memory and to clear the store instruction from the store history table. If a load instruction designates an address for which a store allocate pass has issued but the corresponding store commit pass has not yet been issued, the cache control determines a conflict and the load instruction is reissued. Provision is made for retrieving data from a secondary cache and for clearing store instructions from the store history table upon detection of a branch error.