Pipeline apparatus having pipeline mode eecuting instructions from

Abstract

A pipeline data processor is simultaneously operable in a pipeline mode, a parallel mode and a vector mode which is a special case of the pipeline mode. Each pipeline stage has its own stage program counter. A global program counter is incremented in the pipeline mode. The instruction addresses generated in the global program counter are distributed to those pipeline stages which first become available to perform pipelined data processing. Any given pipeline stage may dynamically switch between pipeline mode and a parallel mode in which the stage program counter counts and supplies instruction addresses independently of any other pipeline stage. A vector mode uses pipeline instructions which are repeated to enable any number of the pipeline stages to participate in vector calculations. In the vector mode, one pipeline instruction address is held in the global program counter to be repeatedly supplied to respective first available pipeline stages until the vector calculations are completed. Other program means are disclosed which effect efficient control of program executions in all three modes and enable the concurrent execution in any mode by any of the pipeline stages.