Semiconductor memory device

Abstract

A semiconductor memory device provided that first data is read out from a first memory cell within a first readout period; and second data is read out from the second memory cell within a second readout period; wherein an amplifier circuit receiving the first and second data, outputting first data signals having first electric potential level corresponding to the first and second data and outputting second data signal having second electric potential level; control circuit, in response to an external control signal, generating a first control signal in each of the first and second readout periods, the first control signal indicating first logic level during an enabling period of time within each of the first and second readout periods, otherwise the first control signal indicating second logic level; a first latch circuit latching the first data signals in the respective first and second readout periods and outputting a first latched data signal at the time of the first control signal indicating the first logic level; a second latch circuit latching the second data signals in the respective first and second readout periods and outputting a second latched data signal at the time of the first control signal indicating the first logic level; and a reset circuit placing the first and second latch circuit in an initial status after the first control signal is transferred from the first logic level to the second logic level in the first readout period and before the first control signal is transferred from the second logic level to the first logic level in the second readout period.