The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 1993

Filed:

Apr. 12, 1990
Applicant:
Inventors:

Shigeru Harada, Hyogo, JP;

Hisao Masuda, Hyogo, JP;

Reiji Tamaki, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02L / ;
U.S. Cl.
CPC ...
257771 ; 257740 ; 257741 ; 257767 ;
Abstract

In a semiconductor device, an impurity diffused layer serving as an active region is formed in a predetermined region of the surface of a semiconductor substrate of silicon, an underlayer insulating film is formed on the semiconductor substrate for the purpose of protecting and stabilizing the surface of the semiconductor substrate, and an interconnection electrically connected to the impurity diffused layer through a contact hole and formed on an Al-Si-Sn alloy, an Al-Si-Sb alloy or alloys having Ti added to the respective alloys, so that occurrence of an alloy pit and a silicon nodule is prevented. In addition, a completed protective film is formed on the interconnection and the underlayer insulating film and an aperture in a bonding pad region is formed in a predetermined region of the completed protective film, so that the interconnection and the bonding pad are electrically connected to each other. The proportion of silicon and other materials in the alloy are controlled to simultaneously avoid alloy pit and silicon nodule defects both at the contact hole and throughout the alloy conductor.


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