The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 1993

Filed:

Mar. 04, 1991
Applicant:
Inventors:

Itaru Kurosawa, Tsukuba, JP;

Hiroshi Nakagawa, Ushiku, JP;

Masahiro Aoyagi, Tsukuba, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01B / ; H01L / ;
U.S. Cl.
CPC ...
505-1 ; 505702 ; 505832 ; 505874 ; 257 31 ; 257 33 ; 257 36 ; 365162 ;
Abstract

One or more superconducting memory cells capable of storing binary values as the presence or absence of a persisting loop current in their superconducting memory loops are connected in series by a circuit current line. This arrangement is provided with a set gate which switches to the voltage state and outputs circuit current from its output terminal to one end of the circuit current line when write command current is supplied to its control terminal and is further provided with a sense gate whose control terminal is series coupled though a capacitance element with the same one end of the circuit current line and whose ground side terminal is connected with the other end of the circuit control line thereby forming through the sense gate a read-out loop for receiving as differential current persisting loop current selectively discharged from the memory loop. The differential current causes the sense gate to switch itself to the voltage state and output a sense current. At least a part of the sense current is supplied to the control terminal of the set gate as rewrite command current. As a result, the read-out of binary values from the superconducting memory loop can be conducted in a manner that is equivalent to nondestructive read-out. As the differential current dissipates automatically over a period of time determined by a prescribed time constant, there remains no residual current which might cause an operational error.


Find Patent Forward Citations

Kurosawa, Itaru. (1993). Josephson memory circuit (U.S. Patent No. 5260264). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5260264

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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