The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 1993
Filed:
Nov. 30, 1990
Jeffrey M Blumenthal, Austin, TX (US);
Nader Vijeh, Cupertino, CA (US);
John M Wincn, Cupertino, CA (US);
Ian S Crayford, San Jose, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A differential receiver incorporated into a MAU which receives both Manchester packets and linkpulses according to the IEEE 802.3 10Base-T standard has polarity detection and correction circuit for automatically detecting a reversed polarity for RD input lines. The differential receiver samples incoming pulses for time, amplitude and pulse width qualification and makes a preliminary polarity determination based upon polarity of such qualified pulses. This preliminary polarity allows a linktest state machine to transition to a link.sub.-- pass state, enabling output drivers of the MAU. Additionally, the linkpulse polarity information initially makes a polarity determination for the entire differential receiver which asserts a FIX POLARITY signal. The FIX POLARITY signal controls a correction circuit which internally remedies reversed input lines. Preferably, the correction circuit internally reroutes the signals. An ETD polarity circuit makes polarity determinations from any ETD information received, as effected by the correction circuit. The ETD polarity circuit independently controls the linkpulse polarity determinations and conflicting determinations are resolved in favor of the ETD polarity circuit. Upon detecting two consecutive, consistent valid ETDs, the ETD polarity circuit locks-in the polarity determinations until a reset or a linkfail condition. The correction circuit effects both Manchester packets and linkpulses, so an incorrectly locked polarity will produce inverted linkpulses which will not allow the MAU to remain in the link.sub.-- pass state. In the linkfail state, the MAU may reestablish the correct polarity.