Bipolar fet read-write circuit for memory

Abstract

A circuit for accessing a column of memory cells in an array of memory cells includes a pair of drivers for activating bit lines for writing data into a selected cell in the column of cells. Each driver includes a bipolar transistor operated with current and voltage applied to a base terminal thereof by a pair of field-effect transistors (FETs) wherein one of the transistors effectively shorts the base terminal to an emitter terminal for elimination of current flow during a state of nonconduction, this FET being overridden by a second FET which applies base current during a state of conduction during writing of the cell. The second FET in each driver is activated by a column address signal applied to a drain terminal thereof, and by a data input signal applied to a gate terminal of the FET to provide for writing during concurrence of the two signals. In the presence of only the column access signal, two sense transistors in branches of a cascode circuit are rendered operative by the column access signal for reading a selected signal. In the absence of both the column access and the data input signals, a restore circuit equalizes voltages of the bit lines, and sets the voltages at a level established by the threshold of an FET having its gate terminal shorted to its drain terminal.