The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 1993

Filed:

Jan. 22, 1992
Applicant:
Inventor:

Toshihiko Kondo, Suwa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 44 ; 437193 ; 437200 ;
Abstract

A production method for an MIS device comprises forming an insulator layer on a semiconductor substrate, depositing a gate electrode having a conductive silicon layer on part of the insulator layer, forming a low-concentration area on part of the surface of the semiconductor substrate using the gate electrode as a mask in a self-aligned manner, depositing a refractory metal layer on the surface of both the gate electrode and insulating film, using a heat treatment process to change part of refractory metal layer which is in contact with gate electrode into a silicide and part of the refractory metal layer which is in contact with the insulator layer into a nitride layer, removing the refractory metal layer leaving that part above surface of gate electrode and a sidewall part a prescribed thickness on the sides of the gate electrode, and forming the source and drain areas on the surface of semiconductor substrate using both the gate electrode and sidewall as a mask. In an alternative method, electrode contact holes are formed in the insulator layer prior to forming the refractory metal layer. The portion of the refractory metal layer above the electrode contact holes is made into a silicide in a heat treatment process. The silicide layer is selectively left behind by the process which removes only the refractory metal.


Find Patent Forward Citations

Kondo, Toshihiko. (1993). Self-aligned method of fabricating an ldd mosfet device (U.S. Patent No. 5254490). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5254490

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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