Subarray architecture with partial address translation

Abstract

The physical organization of a memory cell array in an integrated circuit cache memory system is different from its logical organization because the bit lines of the array are divided into segments to physically divide the memory cell array into sub-arrays, and multiplexing the bit line segments of groups of neighboring bit lines are multiplexed to respective data lines. 'Early' address bits control row decoders which select a row of memory cells in each sub-array to assert data signals on the bit line segments in each sub-array. 'Late' address bits control the multiplexing of the data signals on the bit line segments to the data lines. By segmenting the bit lines, the number of 'late' address bits is increased relative to the number of 'early' address bits to increase the memory access speed in data processing systems that employ virtual addressing but store data in cache memory in association with physical addresses. The 'late' address bits, for example, are a translated portion of a virtual address translated by a translation buffer, and the 'early' address bits are an untranslated portion of the virtual address. Routing problems are avoided by extending the data lines in parallel with the bit lines over regions of the integrated circuit substrate allocated to the memory cells in the array, and forming the data lines in a metalization layer separate from and over a metalization layer of the bit lines. Each data line is multiplexed to multiple bit line segments to eliminate a final multiplexer to input/output lines.