The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 1993
Filed:
Jul. 26, 1991
Daniel C Buck, Hanover, MD (US);
James E Degenford, Dayton, MD (US);
Soong H Lee, Seoul, KR;
Scott A Imhoff, Pasadena, MD (US);
Dale E Dawson, Glen Burnie, MD (US);
Westinghouse Electric Corp., Pittsburgh, PA (US);
Abstract
A semiconductor device has material removed from the back of the substrate and a manufacturing process is provided for manufacturing these devices. In the exemplary embodiment, a GaAs FET chip is formed by a process including the step of etching the GaAs substrate from the back of the chip in a defined removal region to reduce the dielectric constant in the region of the source-to-drain path. A buffer layer of differing material provided between the active layers and the substrate prevents etching of the active layers during the removal process. To allow simplified etching patterns, the source-to-drain path may be laid out on the surface of the chip in a variety of patterns, including 'packed' patterns concentrating a large path area in a small surface area of the chip. Optionally, this buffer layer may also be etched away in a further processing step. An insulating layer of material may be added to the back side of the chip in the etched region to increase structural strength, and a pressure relief ventilation path may be provided connecting the removal region to the outside at an edge or at the surface of the chip.