The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1993
Filed:
May. 22, 1992
Jeffrey M Dodson, Santa Cruz, CA (US);
Christopher T Cheng, Palo Alto, CA (US);
S-MOS Systems, Inc., San Jose, CA (US);
Abstract
A high-speed, area efficient, low-power absolute value arithmetic unit that efficiently produces the absolute value of the difference of two input operands. This arithmetic unit is adaptable to provide other output functions. Further, the arithmetic unit of the present invention may be utilized as a data path element in a high performance floating point arithmetic unit. The present invention includes a propagate and generate block, a carry-chain-and a difference multiplexer. Operands A and B are received by the absolute value arithmetic unit. The propagate and generate block converts operands A and B into propagate signals and generate signals. The carry-chain-receives propagate and generate signals and produces carry-chain-propagate signals and carry-chain-generate signals for every bit, where the most significant carry-chain-generate signal is used to indicate a borrow. The difference multiplexer receives the carry-chain-propagate and carry-chain-generate signals as well as propagate singals from the propagate-and-generate block and produces A-B and B-A. The difference multiplexer then selects either A-B or B-A to produce as an output the absolute value of A-B. The borrow signal acts as the selection means for obtaining the absolute value of A-B. In either case, .vertline.A-B.vertline. is obtained with essentially the same amount of hardware as only one core subtractor. The present invention uses approximately half the amount of hardware as the fastest conventional absolute value arithmetic units and therefore is approximately 50% more compact. The entire absolute value arithmetic unit of the present invention requires essentially the same amount of area as only one conventional adder/subtractor. In addition, the present invention sacrifices no speed to achieve its smaller size and consumes less power than a conventional absolute value subtractor.