The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 1993

Filed:

Dec. 10, 1992
Applicant:
Inventors:

Yukio Ohmamyuda, Sagamihara, JP;

Shigeru Kimura, Yokohama, JP;

Toru Tanabe, Machida, JP;

Takao Seto, Yokohama, JP;

Kazuhisa Iwasaki, Yokohama, JP;

Hideki Kitamura, Yokohama, JP;

Yasushi Senoo, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01C / ;
U.S. Cl.
CPC ...
356-5 ; 356-4 ;
Abstract

To measure a distance between two running vehicles a measurement signal is first generated by irradiating a light beam toward an article to be measured and then receiving the reflected light beam from the article. A reference signal and the measurement signal generated in the above way are input to a digital mix-down circuit which comprises two-stage flip-flop circuit to determine a phase difference between the reference signal and the measurement signal. The apparatus includes a clock delay circuit for delaying the high-going (rising) edge of the measurement signal while the reference signal is going high at an output terminal of a flip-flop circuit on the input side of the digital mix-down circuit, and a data delay circuit for delaying the down-going (falling) edge of the reference signal input into a data terminal of the flip-flop circuit. Usually, the clock delay circuit is electrically connected to the digital mix-down circuit via the data delay circuit, while the data delay circuit is electrically connected directly to the digital mix-down circuit. Alternatively, both the clock delay circuit and the data delay circuit may be electrically connected directly to the digital mix-down circuit.


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