The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 1993

Filed:

Mar. 20, 1992
Applicant:
Inventor:

Creighton S Asato, San Jose, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307443 ; 307451 ;
Abstract

N-input Logic Gates are presented that have a high speed transmission path for a first input logic signal A.sub.1. For an AND Gate embodiment, a logic signal A.sub.1 is applied to an input of a master transmission gate that is transmitting if all of logic signals A.sub.2, . . . , A.sub.N are logic one signals and is otherwise nontransmitting. For an OR Gate embodiment, a logic signal A.sub.1 is applied to an input of a master transmission gate that is transmitting if all of logic signals A.sub.2, . . . , A.sub.N are logic zero signals and is otherwise nontransmitting.


Find Patent Forward Citations

Asato, Creighton. (1993). Fast logic circuits (U.S. Patent No. 5250855). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5250855

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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