The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 1993

Filed:

Feb. 26, 1992
Applicant:
Inventors:

Masaru Yasui, Kobe, JP;

Noriyoshi Uenishi, Kobe, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G / ; G09G / ;
U.S. Cl.
CPC ...
345 98 ; 345211 ; 345214 ;
Abstract

In the case of erasing a display on an active matrix type liquid crystal display which has a source bus drive circuit (16) and a gate bus drive circuit (17), pixel signals for turning OFF pixels of one row are applied to the source bus drive circuit, and at the same time, a clear signal (CL) is provided to the gate bus drive circuit (17), from which a voltage for turning ON transistors (13) provided in association with the respective pixels is applied to gate buses (15.sub.l through 15.sub.m) all at once. A power holding circuit (22) is provided for holding power of an operating power supply (V.sub.1) for a predetermined period of time after the power supply of the display is turned OFF, and a voltage drop detector (24) is provided for detecting the turning OFF of said power supply, and its detection signal is used to produce the clear signal (CL), which is provided to the gate bus drive circuit (17). The gate bus drive circuit responds to the clear signal to apply the voltage for turning ON the transistors (13) of the respective pixels to the gate buses all at once, thereby erasing the display in a short time after the turning OFF of the power supply.


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