The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 1993

Filed:

Apr. 13, 1992
Applicant:
Inventors:

Joseph D Wert, Arlington, TX (US);

Timothy D Davis, Arlington, TX (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307270 ; 307310 ; 307446 ; 307491 ; 307263 ; 307540 ; 307570 ;
Abstract

A signal line driver circuit having an input signal buffer and an open collector output circuit configuration and a method are provided for receiving an input signal and causing the output to pull down the voltage potential of a signal bus line while sinking an output current therefrom at a substantially constant output voltage with a substantially constant input-to-output signal propagation delay variation over variations in operating temperatures. A portion of the output current which is to be sunk from the signal bus line is advantageously used as the current supply for the input signal buffer circuitry. The input signal buffer circuitry uses metal oxide semiconductor field effect transistors in parallel with a bipolar junction transistor to take advantage of their mutually inverse conductivity vs. temperature characteristics, thereby ensuring that the output current sinking capability, output voltage range and input-to-output signal propagation delay variation remain substantially constant over a wide operating temperature range.


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