The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 1993

Filed:

May. 20, 1991
Applicant:
Inventors:

Masayuki Takami, Yamato, JP;

Takehiko Atsumi, Ichikawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J / ; H04J / ;
U.S. Cl.
CPC ...
370112 ; 3701001 ; 361792 ; 361796 ;
Abstract

In a digital signal time-division multiplex apparatus according to the present invention, digital signals transmitted through a plurality of channels are converted into low-order section frame signals in response to sync signals by low-order section frame processing boards provided for their respective channels. The low-order section frame processing boards are arranged in parallel on a mother board at regular intervals. The low-order section frame signals processed by the low-order section frame processing boards are supplied to a high-order section frame processing board and sequentially selected within one frame, thereby generating time-division multiplex signals. The sync signals are generated by a sync signal generating board and transmitted to a sync signal transmitting line formed on the mother board. The sync signal transmitting line is formed so as to transmit the sync signals in a direction in which the low-order section frame processing boards are arranged. The sync signals are supplied to the low-order section frame processing boards through the sync signal transmitting line in a bus line system. The low-order section frame signals generated from the low-order section frame processing boards are transmitted to a plurality of low-order section frame signal transmitting lines formed in the direction in which the sync signals are transmitted, and supplied to the high-order section frame processing board through the low-order section frame signal transmission lines.


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