Enhanced accuracy delta-sigma a/d converter

Abstract

A delta-sigma modulator is provided with a multi-stage shift register coupled to receive as its input the output from a quantizer including an analog integrator. The serial digital output signal train from the shift register is fed back to the input of the integrator and because of the frequency division which takes place, for a given high clock rate, an operational amplifier with a lower gain/bandwidth product may be employed. The invention also includes a signal processor coupled to the output of the delta sigma modulator and which is arranged to provide an adaptive window based, decimation cycle whose exact timing is data dependent. The adaptive windowing process implemented in a microprocessor-based signal processor allows the first occurrence of a proper polarity state transition occurring during a window period to become the termination point of the computation cycle rather than providing a fixed time interval. By doing so, the effective resolution can be increased by an order of magnitude for a predetermined duty cycle.