The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 1993

Filed:

Jan. 31, 1992
Applicant:
Inventor:

Heinz Maeder, Weinfelden, CH;

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
341131 ; 341155 ;
Abstract

This invention relates to a video analog-to-digital converter (ADC) and to a method of digitizing a video analog signal. The video ADC (2) comprises a clock for providing a clock signal (HZ) which clocks a horizontal line rate, dither generating means (10) for generating a dither pattern synchronized with the horizontal clock signal. A preferred dither pattern comprises a staircase sequence of voltage steps, the voltage level of each step being constant for at least one horizontal line. The video ADC further comprises combining means for combining the dither pattern with the analog video signal, digitizing means (4, 6) for converting the combined dither pattern and video signal to a sequence of digital values and correcting means (12) coupled to the digitizing means and the dither generating means for subtracting the dither pattern from the digitized sequence of values so as to generate a sequence of digital values which represent said analog video signal. By superimposing a dither pattern to the analog video signal at the horizontal line rate, the operating point of the ADC can be altered. As a result, step errors of the ADC do not occur at the same horizontal position on a line and are therefore less visible. In a preferred arrangement, the dither pattern is superimposed on a plurality of reference voltage levels generated by bias means (8) and which are applied to the digitizing means so that the dither pattern and the analog video signal are combined in the digitizing means.


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