The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 1993
Filed:
Dec. 30, 1991
Applicant:
Inventors:
Thomas J Kocis, Austin, TX (US);
Darius D Gaskins, Austin, TX (US);
Assignee:
Dell USA, L.P., Austin, TX (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307606 ; 307602 ; 307269 ; 328 63 ;
Abstract
A delay line within an integrated circuit and calibrated by an external time period (calibration clock). The speed of devices in the integrated circuit is assessed using the calibration clock, and this speed then controls how many delay cells within the delay line an input must traverse to trigger the delayed output.
Kocis, Thomas. (1993). Integrated delay line (U.S. Patent No. 5245231). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5245231
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile