The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1993
Filed:
Jan. 29, 1992
Toshifusa Yamada, Kanagawa, JP;
Hiroaki Matsushita, Kanagawa, JP;
Fuji Electronic Co., Ltd., Kanagawa, JP;
Abstract
A semiconductor device includes a housing, a semiconductor element disposed in a lower section inside the housing, an external lead terminal at least partially disposed within the housing, a gelled filler disposed within the housing, the semiconductor element and at least a portion of the external lead terminal being embedded in the gelled filler, a hardened sealing resin layer disposed over the gelled filler, and at least one internal pressure absorbing chamber having a pocket-type sealed space, the internal pressure absorbing chamber passing through the sealing resin layer and being open at an upper surface side of the gelled filler. The semiconductor device prevents a rise in the internal pressure of the housing in response to thermal expansion of the gelled filler sealed within the housing, and the absorption of external moisture by the gelled filler. When the gelled filler expands according to a heat cycle, its increase in volume is absorbed by the internal pressure absorbing chamber to prevent leakage of the gelled filler and the application of stress to the semiconductor element. The absorption of moisture from the air outside of the semiconductor device by the gelled filler is prevented by defining the internal pressure absorbing chamber as a tightly closed pocket-type space to ensure that the semiconductor device is intrinsically resistant to humidity.