Multiprocessor system

Abstract

A cache coherency system and method which switches the data consistency maintenance protocol used for a given piece of shared data at each private cache, automatically depending upon the likelihood or frequency that the processor having the private cache concerned will accesses the given piece of shared data, and the likelihood or frequency that the other processors in a multiprocessor system will access the given piece of shared data. In the preferred embodiment, the present system and method switches between protocols of the invalidate and update types. When the processor corresponding to the private cache concerned is more likely to access the shared data concerned, it is uses the protocol of the update type because it increases the cache hit ratio. On the other hand, while other processors in the system are more likely to access the shared data concerned, it uses the protocol of the invalidate type because it reduces bus traffic required for updating the shared data. In an exemplary configuration, for each piece of shared data in each private cache, the frequency at which the processor corresponding to the private cache concerned accesses the shared data is determined. Further the frequency at which the other processors in the system modify the shared data concerned is determined. The difference between the above frequencies is calculated and compared with a predetermined reference value. The result of the comparing is used to automatically switch the protocols used for the shared data concerned at the private cache concerned.