The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 1993
Filed:
Mar. 15, 1990
Joseph K Farrell, Boca Raton, FL (US);
Jeffrey S Gordon, Centreville, VA (US);
Daniel C Kuhl, Delray Beach, FL (US);
Timothy V Lee, Boca Raton, FL (US);
Tony E Parker, Boca Raton, FL (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Subject burst time division multiplex interface connects circuits which perform 'layer 1 (L1)' line control functions relative to a data communication network with devices which perform 'Layer 2 (L2)' link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organization). The interface is characterized by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable and to be able to devote maximum processing time to performance of L2 tasks required relative to the channels. The channels operate under various communication protocols; e.g. High-Level Data Link Control (HDLC), Link Access Procedure-D (LAP-D), clear voice, etc. Slot time spacings are variable by the L1 circuits to adjust to signalling conditions in the network.