The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 1993
Filed:
Oct. 30, 1991
Yasushi Ooi, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
In a vector calculation unit (31), a multiplication and an addition result register (50 and 53) are connected to a pipeline multiplier (14) and a pipeline adder (15), respectively. A multiplication and an addition result bus (52 and 55) are connected to the multiplication and the addition result registers, respectively. A selector (S1) connects one of an input bus (11) and the multiplication and the addition result buses to the first operand register to which a first multiplication and a first addition operand bus (44 and 45') are connected. A selector (S2) connects one of another input bus (12) and the multiplication and the addition result buses to the second operand register to which second multiplication and second addition operand buses (48 and 49) are connected. A selector (S3) connects one of the first multiplication operand, the multiplication result, and the addition result buses to an input of the multiplier. A selector (S4) connects one of the second multiplication operand, the multiplication result, and the addition result buses to another input of the multiplier. A selector (S5) connects one of the first addition operand, the multiplication result, and the addition result buses to an input of the adder. A selector (S6) connects one of the second addition operand, the multiplication result, and the addition result buses to another input of the adder. A selector (S7) connects one of the first addition operand, the second addition operand, the multiplication result, and the addition result buses to an output bus (13).