The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 1993
Filed:
Mar. 31, 1989
Keith J Bertrand, Sunnyvale, CA (US);
Ampex Systems Corporation, Redwood City, CA (US);
Abstract
The data unpacker receives packed parallel input data words having a fixed width of m bits, and it outputs parallel data words having a variable width of n bits. An input register stores the received words and applies them to a bit shifter. The bit shifter shifts the received data by a number of bit positions indicated by a shift control signal, and the shifted data is output therefrom as a parallel output word having n valid bits. The number n for each output word is received by the unpacker as a binary number. When n.gtoreq.m, a most significant (MSB) bit portion of that number is applied as first MSB control signal. The least significant bit (LSB) portion of n is applied to an adder which adds subsequently received LSB portions to provide a running sum. When the running sum is equal to or greater than m, the adder provides a second MSB control signal, corresponding to the most significant bit of the running sum. The least significant bit portion of the running sum is applied to the bit shifter as the shift control signal. A logic circuit receives the first and second control MSB control signal and it provides in response to either of these signals a READY FOR DATA control signal indicating that the input register is ready to receive the next input word, and a DATA VALID OUT control signal indicating that the bit shifter is ready to output the parallel output word.