Method and apparatus for data transfer between source and destination

Abstract

A computer system is optimized to perform fast block transfers between modules that communicate over a multi-master global synchronous bus. Write operations are speeded up by a destination module sending a 'ready-to-accept-data' signal before each write request. During a given clock period during which a source module delivers a data word to the bus, the destination module asserts this 'ready' signal to indicate to the source module that the destination module is ready for the source module to deliver another word during another, subsequent clock period. The source module can deliver one word per clock period, and the destination module can receive one word per clock period. During a block write, only the starting address for the first word transferred is transmitted, with a counter at both source and destination modules counting each word transferred. Part of the address bus is not used for addresses and instead is used for data. Local memory is accessed in each module at the rate of one access per clock period. The bus performs one transfer per clock cycle, with successive transfers pipelined on the bus to minimize dead cycles.