The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 1993
Filed:
Dec. 20, 1991
Andreas G Papaliolios, Sunnyvale, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A sense amplifier that is calibrated prior to each memory read operation to reduce the effects of offsets in a differential input stage. A differential amplifier output signal is connected to a switched inverter by a coupling capacitor. During an equalization time period, the inverter is short circuited between its input and output and is biased to a high gain, trip point. During such time period, the differential amplifier has a bit line input and a reference voltage input, both precharged to a predetermined voltage. The output of the differential amplifier is coupled to a low impedance amplifier. The low impedance amplifier provides an output midway between the supply voltage and ground. The coupling capacitor is charged during the equalization period, but when the bit line voltage and reference voltage are applied to the differential amplifier, the coupling capacitor is charged or discharged, depending upon the state of the memory readout signal. The change in the charge on the coupling capacitor moves the switched inverter from its trip point to an output logic state, also depending upon the memory readout signal. The sense amplifier is thus automatically calibrated, and provides a high speed sensing of memory signals.