The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 1993

Filed:

Nov. 05, 1991
Applicant:
Inventors:

Michael R Feldman, Charlotte, NC (US);

Iwona Turlik, Raleigh, NC (US);

Gretchen M Adema, Durham, NC (US);

Assignee:

MCNC, Research Triangle Park, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B / ; G02B / ; G02B / ; G11C / ;
U.S. Cl.
CPC ...
359 19 ; 359 15 ; 385 14 ; 385 37 ; 257737 ; 250551 ; 365 64 ;
Abstract

A multichip module having high density optical and electrical interconnections between integrated circuit chips. An optically transparent substrate is positioned overlying an array of integrated circuit chips mounted on a mounting substrate. The mounting substrate may include a heat sink to remove excess heat from the integrated circuit chips. The multichip module includes integrated circuit chips having optical detectors and optical transmitters to establish optical interconnections therebetween. A hologram is positioned in the optical path between the optical transmitters and the optical detectors. A planar mirror is preferably positioned opposite the hologram to direct the optical beams. The optically transparent substrate also includes an array of electrical contact pads to establish electrical connections with corresponding electrical contact pads on the underlying integrated circuit chips. A pattern of electrical interconnection lines is provided on at least one of the mounting substrate or the transparent substrate to electrically interconnect predetermined ones of the integrated circuit chips.


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