The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 1993

Filed:

May. 18, 1992
Applicant:
Inventors:

Christine Anceau, Saint Roch, FR;

Jean-Baptiste Quoirin, Tours, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437230 ; 437193 ; 437228 ; 437904 ; 427 98 ;
Abstract

A metallization layer forming a bonding pad is formed on a diffused region of a semiconductor substrate for making electrical connection to the diffused region. A polysilicon layer of the same conductivity type as the diffused region is formed on the diffused region, overlapping onto sidewalls and peripheral portions of a silicon oxide mask. A two-layer metallization layer comprising a first nickel layer and an overlying gold layer covers the polysilicon layer. The semiconductor device is formed by diffusing an impurity into the upper surface of a semiconductor substrate using a silicon oxide mask. A doped polysilicon layer is formed on the diffused region, overlapping onto sidewall portions and extending up onto the silicon oxide mask layer. The substrate is immersed in a metal-plating electroless bath to form layers of nickel and gold on conductive portions of the substrate including on the polysilicon and on a face of the substrate opposite the polysilicon layer. The substrate is selectively etched to remove contaminants from the silicon oxide mask introduced during immersion in the electroless bath. The device is then annealed at a suitable temperature. With a plurality of devices formed on a single wafer, the wafer is scored and diced to separate the devices for individual packaging.


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