The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 1993

Filed:

Oct. 30, 1990
Applicant:
Inventor:

Hitoshi Takagi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395400 ; 395425 ; 364D / ; 364D / ;
Abstract

In an address translation device (11) used in combination with a main memory (12) in translating an input virtual address into an output real address, an address translation buffer (15) is for memorizing not only a plurality of buffer virtual addresses (BVA) and a plurality of buffer real addresses (BRA) corresponding to respective buffer virtual addresses but also buffer presence bits (BP) corresponding to respective buffer real addresses to indicate presence or absence of a datum of a memory real address in the main memory in correspondence to each of the buffer real addresses. A comparison control circuit (17) compares the input virtual address with a particular one of the buffer virtual addresses, that corresponds to the input virtual address to make the address translation buffer produce, as the output real address, a particular one of the buffer real addresses, which corresponds to the particular buffer virtual address when the input virtual address coincides with the particular buffer virtual address.


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