The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 1993
Filed:
Jun. 10, 1991
Alcatel N.V., Amsterdam, NL;
Abstract
A test device for testing integrated electronic chips (EC) includes: a first processor; an interface for interfacing the first processor with a plurality of other circuits; and a second processor coupled to the first processor. In the test device, at least one of the plurality of other circuits is formed on the integrated electronic chip being tested. The interface includes a first scan path having a first string of first cells formed on the integrated electronic chip. The first string of first cells includes a plurality of serially connected first read buffers, a respective one of the first read buffers being provided in each first cell, for latching data and for transferring data between the at least one circuit of the plurality of other circuits and the first processor. A second scan path includes a second string of second cells, which includes a plurality of serially connected second read buffers, a respective one of the second read buffers being provided in each second cell for latching data and for transferring data between the second processor and the second scan path. The second processor and the first processor are coupled together via a serial interconnection connected between the first and second read buffers. A data transfer device serially transfers latched data from the first read buffer to said second read buffer and visa-versa, at a predetermined transfer rate such that one data transfer is provided at each of a plurality of processor steps of said second processor.