Packet switch suitable for integrated circuit implementation

Abstract

A packet switch for high-speed synchronous multiplexing of voice and picture communications collectively. The packet switch uses among other things an input multiplexer, and output demultiplexer, and a single buffer memory divided into memory areas connected to multiple input and output lines. The subdivided buffer is controlled by counters rather than a more complicated address exchanger. A second embodiment eliminates the need for an output demultiplexer because of individual read/write control of the buffer units. A third embodiment includes a bidirectional bus between an input buffer and an output buffer. A fourth embodiment uses a more economical unidirectional bus. The unidirectional bus can be limited to a part of an input packet to permit Large Scale Integration (LSI). In the LSI configuration, address filters may be replaced with a centralized address controller, and the buffer can consist of FiFo memory units or RAM units.