Speed detector device for elevator

Abstract

A speed detector device capable of making speed measurements of an elevator in its relatively slow speed region comprises a pulse generator generating two-phase pulse signals with a predetermined phase difference between both signals, in a period according to the rotational speed of a motor, a pulse processing circuit for outputting corresponding triggers in response to the rising edge and the falling edge of each of the pulse signals generated by the pulse generator, a timer counter, latches for latching the output of the timer counter at the timing of the triggers, and calculating circuit for calculating the period of the pulse signals based on the timer counter output and for calculating the speed of the elevator based on the period calculated. The above arrangement allows data to be latched not only at the rising edge of the one pulse signal, but also at the falling edge of the same pulse signal and the rising and falling edges of the other pulse. Thus, even if no rising edge exists during a CPU read cycle, speed detection is possible at the other rising edges. Thus, accurate speed measurements are achieved.