Fault tolerant processor/memory architecture

Abstract

A primary processor provides control, address and data signals to a shadow comparison ASIC which also receives corresponding signals from a shadow processor running in delayed lock step with respect to the primary processor. The primary processor is coupled to a system CPU bus which communicates through a memory interface with a DRAM memory. An EDC circuit generates EDC syndrome bits with respect to data written by the primary processor into the memory through the interface. The EDC syndrome bits are stored in memory along with the data. The shadow comparison ASIC includes an identical EDC circuit for generating comparable syndrome bits from the data transmitted from the primary processor to the memory when in the write mode and from the data transmitted from the memory to the primary processor when in the read mode. The syndrome bits generated in the ASIC are compared with those generated at the memory to detect discrepancies indicative of failure when in the write mode and with those stored in the memory to detect discrepancies indicative of failure when in the read mode.