The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 1993
Filed:
Jan. 28, 1992
Applicant:
Inventor:
Charles C Stearns, Palo Alto, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364757 ;
Abstract
A digital multiplier is configured from a number of identical circuit 'slices' with interconnecting signals arranged such that the need for large wiring channels is eliminated. The resulting multiplier, a hybrid of tree and array multipliers, has many of the space saving characteristics of array multipliers, with many of the speed advantages of tree multipliers. Various parameters of the design are flexible and may be changed by the designer to make speed versus size tradeoffs. The multiplier may be either pipelined or non-pipelined.