The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 1993
Filed:
Jun. 05, 1991
Applicant:
Inventor:
Sakae Itoh, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307480 ; 307590 ; 307601 ;
Abstract
A delay clock signal is generated by delaying an input clock signal by a predetermined time interval with a delay circuit, and is subjected to frequency division with a frequency divider circuit to generate a reference clock signal. This delay clock signal and the input clock signal are provided to a flip-flop to generate a first electronic state signal when the input clock signal turns from 'High' to 'Low', and a second electronic state signal when the reference clock signal turns from 'High' to 'Low', and to electronically activate a control object during the time the second electronic state signal is inputted.