The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 1993
Filed:
Apr. 01, 1992
Darrel D Donaldson, Lancaster, MA (US);
Daniel Wissell, Acton, MA (US);
Digital Equipment Corporation, Maynard, MA (US);
Abstract
A power supply interlock technique for an electronic system which uses metal oxide semiconductor (MOS) logic circuits require two or more different supply voltages, and where each circuit board module contains its own power supplies. An open-collector enable signal is both controlled and sensed by each of the modules. The enable signal is set true when all of the supplies in the system are operating properly. However, the enable signal is set false by any one of the modules if one of the higher voltage supplies on that module is malfunctioning. The enable line also controls the lower voltage power supplies in each module. None of the lower voltage power supplies is thus permitted to operate until the enable line is set true, which occurs only when all of the modules indicate they have an operating high voltage supply available. As a result, latch-up of parasitic transistors in the circuits which drive logic signals on a system bus is avoided.