The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 1993
Filed:
Jul. 24, 1992
David B Harris, Columbia, MD (US);
Scott P Karr, Columbia, MD (US);
Stephen J Reinhart, Annapolis, MD (US);
Abstract
The difficulty with integrating packaged devices into a dual composite module design for wafer scale devices is the height difference between the WSI and packaged devices a typical wafer scale device is 0.025 (in) high while typical packaged VLSI components are 0.080 (in) or more. This leaves little room for the other 5 layers of interconnect boards and PCI layers required for the dual composite module. The solution is that the PWB on the side of the composite heat sink has been shortened to support only the wafer scale device on the heat sink. This eliminated PWB thickness and PCI interfaces from the side with the VLSI components. Also 3-P connectors are made with a pressure contact interconnecting (PCI) board.