The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 1993
Filed:
Sep. 16, 1991
Allen A Bahr, Tucson, AZ (US);
Tony R Larson, Tucson, AZ (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The current mode sample-and-hold circuit includes a differential amplifier having a non-inverting input coupled to a first leg of a current mirror from which a first current to be sampled is drawn. An inverting input of the differential amplifier is coupled to its output and further coupled to a capacitor through a sample hold switch. The first current drawn from the first leg of the current mirror causes the capacitor to charge, through the differential amplifier. The charged capacitor is coupled to the current mirror and biases the current mirror so as to provide the required first current. Opening the sample hold switch causes the capacitor to maintain a bias level determined by the first current. The bias signal in turn causes a mirrored current flowing in a second leg of the current mirror to be maintained, even in the absence of the first current. Thus an input current is sampled and a corresponding output current is provided. The capacitor operates in a feedback loop for improving accuracy. Furthermore, the capacitor is isolated from both the input and output providing high frequency capability. Alternatively, the sample hold switch may be replaced by a diode for providing a peak detector function.