Cache controller for maintaining cache coherency in a multiprocessor

Abstract

A data processing system that includes a plurality of processors with at least a portion of this plurality of processors each individually connected to a cache memory for storing data for that processor. Each cache memory includes a cache controller that is connected to a bus. Each controller includes a circuit for independently storing a data coherency procedure indicator indicating that the controller will perform one of two or more data coherency procedures. According to one procedure, when data is updated in a cache memory, corresponding data is updated in another cache that stores the corresponding data. In a second data coherency procedure, when data is updated in one cache, the corresponding data stored in another cache is invalidated. The individual and independent storing of the coherency procedure indicator enables each cache to perform either one or the other data coherency procedure without interfering with the data coherency procedures performed by other caches in the data processing system. Furthermore, the cache that is updating data provides an updating signal on the bus, which is received by the other caches on the bus. The controllers of those caches will then either update or invalidate any corresponding data in accordance with those caches stored coherency procedure indicators.