The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 1993
Filed:
Nov. 29, 1991
Applicant:
Inventor:
Toshimasa Usui, Suwa, JP;
Assignee:
Seiko Epson Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01P / ; H01P / ;
U.S. Cl.
CPC ...
333-1 ; 333238 ;
Abstract
A method of minimizing line capacitance for transmission lines in integrated circuits is presented to decrease the device performance problems of time delay and noise generation caused by capacitive coupling effects. The prime objective is to decrease the high line capacitance associated with such long length lines as clock lines, buslines and analogue signal lines as well as designated lines requiring low line capacitance. A procedure for applying CAD to such a design concept is also indicated. Although the present embodiments refer to transmission lines within one layer of an IC, the basic concept outlined is applicable also to multilayer designs.