The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 1993

Filed:

Mar. 19, 1992
Applicant:
Inventor:

Yasuhiro Ishii, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307475 ; 307446 ; 307449 ; 307473 ;
Abstract

A level conversion circuit includes first to nth circuits, each having an input terminal and first to nth output terminals where n is an integer, and first to nth signal lines coupled to the first to nth circuits. Each of the first to nth circuits comprises a part for outputting a first voltage to the first output terminal and outputting a second voltage to the second to nth output terminals other than the first output terminal when an input signal applied to the input terminal is at a first level and for maintaining the first to nth output terminals in high-impedance states when the input signal is at a second level different from the first level. The first output terminal of each of the first to nth circuits is connected to one of the first to nth signal lines so that first output terminals of the first to nth circuits are connected to mutually different signal lines. The second to nth output terminals of each of the first to nth circuits are connected to (n-1) signal lines other than the one of the first to nth signal lines to which the first output terminal is connected.


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