The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 1993
Filed:
Oct. 16, 1991
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A semiconductor device is disclosed which comprises a normally-off first MOSFET, a normally-off second MOSFET connected between the gate and source of the first MOSFET, a diode connected between the gate and source of the second MOSFET, a resistor and an optoelectric transducer array, both of which are connected in parallel with each other between the gate and drain of the second MOSFET, wherein all of the components are formed on a single semiconductor chip. Also disclosed is a semiconductor device comprising a normally-off first MOSFET, a normally-on second MOSFET connected between the gate and source of the first MOSFET, a first resistor and a diode, both of which are connected in series between the source and drain of the second MOSFET, a second resistor connected between the gate and source of the second MOSFET, an optoelectric transducer array connected between the gate of the second MOSFET and the terminal which is positioned between the first resistor and the diode, wherein all of the components are formed on a single semiconductor chip. Further disclosed is a method for manufacturing a semiconductor device comprising a normally-off first MOSFET, a normally-off second MOSFET connected between the gate and source of the first MOSFET, a diode connected between the gate and source of the second MOSFET, a resistor and an optoelectric transducer array, both of which are connected in parallel with each other between the gate and drain of the second MOSFET.