The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 1993
Filed:
Nov. 04, 1991
Keisuke Okada, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
Disclosed is a process for preparing a multi-layer printed wiring board including the step of forming a through hole and an external layer circuit on a laminated board of double-sided or multi-layer construction. Then the laminated board is coated over the whole front and back surfaces with a paste-like heat-resistant resin, simultaneously filling the through hole with a resin. A copper foil is disposed on the whole front and back surfaces of the laminated board. Next, the arrangement is heated and pressure-molded in a vacuum. The copper foil is then removed to form an intermediate laminated board. Then, multilayer molding of at least two sets of intermediate laminated boards with a prepreg interposed therebetween is preformed via a step of heat and pressure-molding. In using the penetrated through hole as the divided via hole, there is no longer a restriction of the thickness of the respective divided via holes on the same lattice point. Thus, it has become possible to use the via holes in a higher multilayer board, dramatically improving wiring capacity over the prior art divided via holes.