The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 1993
Filed:
Jul. 20, 1992
Applicant:
Inventors:
Daniel Watkins, Los Altos, CA (US);
Jeffrey A Werner, Santa Clara, CA (US);
H I Hweizen, San Jose, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364489 ; 364578 ;
Abstract
A system for interactive, design and stimulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results, simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time.