The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 1993

Filed:

Apr. 21, 1992
Applicant:
Inventor:

Hisakazu Miyatake, Nara, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437194 ; 437-9 ; 437173 ; 437188 ; 437190 ;
Abstract

A method for forming a metallization layer for wiring in a semiconductor integrated circuit, which includes the steps of: (1) forming an interlayer insulator on a Si substrate used to form a semiconductor device; (b) forming a contact hole extending through the interlayer insulator down to a surface of the Si substrate on which surface is deposited a TiW or TiN film; (c) depositing an Al or Al alloy film on the interlayer insulator as well as on the TiW or TiN film in the contact hole; and (d) in a high-pressure inert gas atmosphere, heating the thus processed substrate to a temperature at which the Al or Al alloy film is fused, while vibrating the entire substrate with ultrasonic waves.


Find Patent Forward Citations

Miyatake, Hisakazu. (1993). Method for forming metallization layer of wiring in semiconductor (U.S. Patent No. 5219790). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5219790

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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