The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 1993
Filed:
Mar. 30, 1992
David K-Y. Liu, Dallas, TX (US);
Kueing-Long Chen, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
In one described embodiment of the present invention, a method for manufacturing a sublithographic semiconductor feature is disclosed. This method comprises: depositing a feature material on a substrate (14); depositing and patterning a resist material (20) over said feature material; vertically, anisotropically etching said feature material to form a feature pattern (18) with substantially vertical sidewalls underlying said resist material pattern (20); isotropically etching said feature pattern (18) such that said feature pattern (18) sidewalls are undercut from beneath said resist material pattern (20) to form a reduced geometry feature (18) whereby said reduced geometry feature (18) has a geometry less than that of the overlying resist material pattern (20). Another described embodiment comprises an antifuse formed by the above method wherein the antifuse dielectric (24) is a nitride-oxide (N-O) layer. The further advantage gained using this structure is that the programming voltage required is substantially reduced due to the asymmetric current conduction characteristics of the N-O dielectric. This lower programming voltage enhances the scalability of this structure to smaller processes as the need for high voltage transistors is reduced. Other devices, systems and methods are also disclosed.