Nervous clock signal generator for video recorder

Abstract

A video recorder for recording composite video signals includes an analog to digital converter for digitizing samples of the composite video signal being recorded. A sync separator separates horizontal synchronizing information from the composite video signal being recorded. Filtering separates the chrominance information portion of the composite video signal being recorded, and a down-converter mixes that separated chrominance information with a nervous carrier signal thereby to generate a color-under signal. A controlled oscillator generates a succession of pixel clock signals at a rate the frequency and phase of which are determined in accordance with an oscillator control signal, the rate being more than twice the frequency of the nervous carrier signal and setting the rate of the sampling by the analog to digital converter. A counter counts the number of pixel clock signals supplied by the controlled oscillator, and a frequency divider divides the count by a prescribed factor. A discriminator determines when the resulting submultiple of the count differs in frequency or phase from the horizontal synchronization separated from the composite video signal being recorded, to develop an error signal that is low-pass filtered to generate the oscillator control signal. This completes a phase-lock loop connection including the controlled oscillator, the counter, the frequency divider, the discriminator and the low-pass filter, which loop governs sampling during the analog to digital conversion of the composite video signal being recorded. The nervous carrier signal is derived from this same phase-lock loop.