The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 1993
Filed:
Jul. 31, 1991
Tomohiro Kurozumi, Moriguchi, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
An AND circuit having a first input terminal, a second input terminal and an output terminal, and is defined by a P-channel MOS FET, an N-channel MOS FET, a NPN bipolar transistor and a resistor. The P-channel MOS FET has a source connected to the first input terminal and a gate connected to the second input terminal. The N-channel MOS FET has a gate connected to the second input terminal, a source connected to the ground and a drain connected to the drain of the P-channel MOS FET. The transistor has a base connected to the drain of the P-channel MOS FET, and the collector-emitter thereof connected between an electric power supply line and the ground. The resistor is connected in series to the collector-emitter of the transistor. One end of the resistor is connected to the output terminal. The AND circuit has less MOS FETs so that the layout area can be reduced.