The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 1993

Filed:

Nov. 12, 1991
Applicant:
Inventors:

John M Neilson, Norristown, PA (US);

Frederick P Jones, Mountaintop, PA (US);

Joseph A Yedinak, Wilkes-Barre, PA (US);

Assignee:

Harris Corporation, Melbourne, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257327 ; 257335 ; 257343 ; 257345 ; 257657 ;
Abstract

In a power FET composed of a substrate having upper and lower surfaces and having a semiconductor body of a first conductivity type, the body providing a current flow path between the upper and lower surfaces and having at least one body region which extends to said upper surface; and at least one base region extending into the substrate from the upper surface, the base region being of a second conductivity type opposite to the first conductivity type and having an upper portion located adjacent the upper surface of the substrate and a lower portion separated from the upper surface of the substrate by the upper portion, the upper portion defining a channel which is disposed in the current flow path adjacent the upper surface of the substrate, and the FET further having an insulated gate disposed at the upper surface above the body region, an impurity layer region extends into the channel from the upper surface of the substrate for giving the channel a lower impurity density than the lower portion of the base region.


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