The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 1993
Filed:
Feb. 28, 1990
Hideki Yoshizawa, Tokyo, JP;
Hiroki Iciki, Tokyo, JP;
Hideki Kato, Tokyo, JP;
Kazuo Asakawa, Kanagawa, JP;
Yoshihide Sugiura, Tokyo, JP;
Hiroyuki Tsuzuki, Kanagawa, JP;
Hideichi Endoh, Kawasaki, JP;
Takashi Kawasaki, Kawasaki, JP;
Toshiharu Matsuda, Kawasaki, JP;
Hiromu Iwamoto, Yokohama, JP;
Chikara Tsuchiya, Machida, JP;
Katsuya Ishikawa, Kawasaki, JP;
Fujitsu Limited, Kanagawa, JP;
Abstract
An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors. The weight correcting unit calculates a correct weight using a gain based on the detection output voltage output from the second analog bus. A weight memory stores the weight corrected by the weight correcting unit.